Designing and fabricating electronic systems typically involves many steps, known as a design flow. The particular steps of a design flow often are dependent upon the type of electronic system being designed, its complexity, the design team, and the fabricator or foundry that will manufacture the electronic system. The design flow typically starts with a specification for a new electronic system, which can be transformed into a logical design. The logical design can model the electronic system at a register transfer level (RTL), which is usually coded in a Hardware Design Language (HDL), such as System Verilog, Very high speed integrated circuit Hardware Design Language (VHDL), System C, or the like. The logical design of the electronic system can be analyzed to confirm that it will accurately perform the functions desired for the electronic system. This analysis is sometimes referred to as “functional verification.”
After the accuracy of the logical design is confirmed, it can be converted into a device design by synthesis software. The device design, which is typically in the form of a schematic or netlist, describes the specific components, such as transistors, resistors, and capacitors, which can be used in the electronic system, along with their interconnections. This device design generally corresponds to the level of representation displayed in conventional circuit diagrams.
A designer, for example, using a place-and-route tool, can place portions of the device design relative to each other in a geographic design environment. While these device design portions can correspond to segments of code in a hardware description language, they typically are shown in the geographic design environment as blocks representing components of the electrical system. Once the blocks have been placed relative to each other, wiring lines can be routed between the blocks. These wiring lines represent the interconnections, such as data signal interconnections and clock signal interconnections, which can be formed between the components of the electrical system.
This place-and-route process is usually iterative, with the placement of the device design components and routing of the wiring lines being analyzed to determine whether they conform to the specification of the electronic system. For example, the place-and-route tool can analyze the placement of the device design components and routing of the wiring lines to determine signal integrity for the various wiring lines. Signal integrity refers to the degree of immunity a device design has to crosstalk effects, for example, caused by parasitic capacitance between adjacent channels, wires, or nets in the device design. This cross-coupling can cause changes in signal slew rates and delays that can affect timing closure for the device design, and also cause signal glitches that can induce logic errors.
Delay computation of signaling on a wiring line suffering from crosstalk—often represented as capacitive-couple Resistance-Capacitance (RC) network—is a specific type of analysis performed by the place-and-route tool. This type of analysis considers both variations in signal delay on the wiring line, sometimes called a victim channel, as well as a presence of noise bumps from one or more aggressor channels and variations on when the noise bumps can arrive on the victim channel. The place-and-route tool typically iteratively simulates the device design with multiple different temporal alignments of signal switching events on the victim channel and signal switching events on one or more aggressor channels that can produce crosstalk noise on the victim channel in order to arrive at worst and best signal delay on the victim channel. Since today's electronic systems can be small geometry and include low supply voltage scenarios, each simulation of the device design, includes a very accurate and resource-intensive analysis to avoid missing a potential timing violation—which can result in a failure of the electronic system.